Phase detector with minimized phase detection error

ABSTRACT

A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

This is a continuation of application Ser. No. 08/582,045, filed on Jan.2, 1996, which is a continuation of application Ser. No. 08/197,641,filed on Feb. 15, 1994 now abandoned.

FIELD OF THE INVENTION

The present invention pertains to the field of phase detection circuits.More particularly, this invention relates to a phase detector thatrelatively accurately detects the phase difference between two inputsignals having different voltage swing characteristics, wherein thephase detector substantially minimizes the phase detection error arisingfrom parasitic capacitance.

BACKGROUND OF THE INVENTION

Phase detection circuits are typically used in computer systems andother electronic systems for detecting the phase difference between twoinput signals. For example, in a phase locked loop (“PLL”) system, it isfrequently desirable to generate a periodic signal waveform that is in aquadrature (i.e., 90 degree) phase relationship with a reference signal.This typically requires a phase detection circuit in the PLL system todetect any departure from the desired quadrature phase relationshipbetween the two signals. The detected departure from the desired phaserelationship between the two signals is typically referred to asquadrature phase error.

When the phase detection circuit detects the quadrature phase error, theamount of the quadrature phase error is then supplied to other circuitsof the PLL system. These other circuits of the PLL system thencompensate for the quadrature phase error of the two signals such thatthe desired quadrature phase relationship between the two signals ismaintained. As is known, a PLL system is typically used to maintainstable frequency and phase characteristics of an input signal.

One type of prior art phase detection circuit for detecting thequadrature phase error of two signals is an exclusive-OR gate logiccircuit. The exclusive-OR gate logic circuit detects the quadraturephase error by causing its average output voltage to be proportional tothe quadrature phase error.

Disadvantages are, however, associated with the prior art exclusive-ORgate type quadrature phase detector. One disadvantage is that the priorart exclusive-OR gate type quadrature phase detector typically requiresthat its input signals have substantially similar voltage swingcharacteristics. If the input signals have different voltage swings, theaverage output voltage of the exclusive-OR gate typically cannotproperly reflect the quadrature phase error detected.

Another disadvantage associated with such a prior art detector is thatthe prior art detector typically cannot accurately detect the quadraturephase error. This is often due to the fact that phase detection errorstypically occur in the circuit during phase detection. One contributorto the phase detection errors is the parasitic capacitance in thecircuit. Because of the unpredictable nature of the parasiticcapacitance, it is often relatively difficult to compensate for thephase detection errors that arise from the parasitic capacitance.

SUMMARY AND OBJECTS OF THE INVENTION

One of the objects of the present invention is to provide a phasedetector that accurately detects the phase difference between two inputsignals having different voltage swing characteristics.

Another object of the present invention is to provide a phase detectorthat substantially minimizes the phase detection error induced by theparasitic capacitance.

Another object of the present invention is to provide a phase detectorthat minimizes the phase detection error of the circuit by compensatingfor the parasitic capacitance that causes the phase detection error.

A further object of the present invention is to provide a phase detectorfor detecting the phase difference between a full voltage swing periodicsignal and a low voltage swing quasi-differential or fully differentialperiodic signal, and for providing compensation for phase detectionerrors arising from parasitic capacitance such that substantiallyaccurate measurement of the phase difference of the two signals can beobtained.

A phase detector is described that includes a load circuit that presentsa high differential impedance and a low common mode impedance. The loadcircuit is coupled to (1) a power supply and (2) a first node and asecond node. The first and second nodes form an output of the phasedetector. A capacitive circuit has (1) a first capacitor coupled to thefirst node and ground and (2) a second capacitor coupled to the secondnode and ground. A first circuit is coupled to (1) the first and secondnodes and (2) ground for detecting a phase difference between a firstinput signal and a second input signal. A second circuit is coupled to(1) the first and second nodes and (2) ground for detecting the phasedifference between the first and second input signals and for minimizingphase detection error of the first circuit such that the phasedifference between the first and second input signals can be detectedwith minimized phase detection error. Each of the first and secondcircuits receives the first and second input signals and a referencesignal. The first and second circuits are cross-coupled such that anerror current generated by the second circuit cancels that generated bythe first circuit so that the phase detector detects the phasedifference between the first and second signals with minimized phasedetection error.

A phase detector is described that includes a load circuit that presentsboth a high differential impedance and a low common mode impedance. Theload circuit is coupled to (1) a power supply and (2) a first node and asecond node. The first and second nodes form an output of the phasedetector. A capacitive circuit includes (1) a first capacitor coupled tothe first node and ground and (2) a second capacitor coupled to thesecond node and ground. A first circuit is coupled to (1) the first andsecond nodes and (2) ground for detecting a phase difference between afirst input signal and a second input signal. The first circuit has afirst transistor coupled to the first node and a third node, a secondtransistor coupled to the second and third nodes, and a third transistorcoupled to the third node and ground via a first current source. Thefirst transistor receives the first input signal. The second transistorreceives a reference signal. The third transistor receives the secondinput signal. The first and second signals have different voltage swingcharacteristics.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitedto the figures of the accompanying drawings, in which like referencesindicate similar elements and in which:

FIG. 1 illustrates a phase detector in accordance with one embodiment ofthe present invention;

FIG. 2 illustrates the waveform of the output signal of the phasedetector of FIG. 1 in view of various input signals;

FIG. 3 is-a circuit diagram of a phase detector in accordance withanother embodiment of the present invention;

FIG. 4 illustrates the waveform of the output signal of the phasedetector of FIG. 3 in view of various input signals.

FIG. 5 shows a comparator that can be used in conjunction with theoutput signal produced by the circuits of FIGS. 1 and 3.

DETAILED DESCRIPTION

FIG. 1 illustrates the circuit of a quadrature phase detector 10 thatimplements one embodiment of the present invention. Phase detector 10 ofFIG. 1 detects the quadrature phase error between first and second inputsignals that are in quadrature phase relationship and that havedifferent voltage swing characteristics. FIG. 3 illustrates the circuitof another quadrature phase detector 40 that implements anotherembodiment of the present invention. Phase detector 40 minimizes thephase detection error induced by the parasitic capacitance. Phasedetectors 10 and 40 will be described in more detail below.

Phase detector 10 shown in FIG. 1 includes transistors 11 through 14 and19 through 21. For one embodiment, transistors 11-14 and 19-21 are metaloxide semiconductor field effect transistors (“MOSFETs”) and are in acomplementary metal oxide semiconductor (“CMOS”) configuration. Forother embodiments, transistors 11-14 and 19-21 can be N-channel MOSFETtransistors or P-channel MOSFET transistors. For alternativeembodiments, other devices, such as bipolar transistors, may be used.

For one embodiment shown in FIG. 1, transistors 11-14 are P-channeltransistors that are connected as current sourcing transistors between apower supply voltage V_(DD) and nodes 15 and 16. Alternatively,transistors 11-14 can be N-channel transistors or bipolar transistors.

Transistors 11-14 together constitute the load of phase detector 10.Transistors 11-14 present a high differential impedance between nodes15-16 and a low common mode resistance from the power supply V_(DD) tonodes 15-16. Diode connected transistors 11-12 serve as a low commonmode resistance between the power supply V_(DD) and nodes 15-16.Transistors 11-12 also constitute a positive differential loadresistance between nodes i 5 and 16. Transistors 13-14 constitute anegative differential load resistance between nodes 15 and 16. Thenegative differential load resistance cancels the positive differentialload resistance. As a result, transistors 11-14 together present thehigh differential load resistance between nodes 15 and 16. Theconnection of transistors 11-14 is described below.

Alternatively, other types of load circuits can be used in phasedetector 10 between the power supply V_(DD) and nodes 15-16. Inaddition, the load formed by transistors 11-14 can be any other kind ofhigh differential impedance load circuit.

The drain of transistors 1 1 -14 are connected to node 15 and the drainof transistors 12 and 13 are connected to node 16. Each of transistors11-12 has its gate coupled to its drain. In addition, the gate oftransistor 13 is connected to the gate of transistor 11, and the gate oftransistor 14 is connected to the gate of transistor 12. Because thegates of transistors 11 and 13 are connected together and the gates oftransistors 12 and 14 are connected together, transistor 13 mirrors thecurrent through transistor 11 and transistor 14 mirrors the currentthrough transistor 12. In other words, transistors 11 and 13 constitutea current mirror and transistors 12 and 14 constitute another currentmirror. By mirroring the current flowing through transistor 11 to node16 and by mirroring the current flowing through transistor 12 to node15, each of nodes 15-16 receives substantially the same amount ofcurrent and no differential current is generated. This therefore causestransistors 11-14 to present a high differential load resistance becausethe negative differential load resistance generated by transistors 13-14cancels the positive differential load resistance generated bytransistors 11-12.

For one embodiment, transistors 11-14 are substantially identical insize such that the negative differential load resistance generated bytransistors 13-14 cancels the positive differential load resistancegenerated by transistors 11-12.

Nodes 15-16 form the output of phase detector 10. A first capacitor orcapacitance 17 is connected between ground and node 15 and a secondcapacitor or capacitance 18 is connected to node 16 and ground. For oneembodiment, capacitors 17 and 18 have substantially equivalentcapacitance. For one embodiment, capacitors 17 and 18 include parasiticcapacitances of transistors 11-14 at nodes 15-16, respectively.Alternatively, capacitors 17 and 18 may or may not comprise parasiticcapacitances, such as those of transistors 11-14 at nodes 15-16,respectively.

The circuit of FIG. 1 has a pair of transistors 19 and 20 that receive aquasi-differential input signal comprising signals V_(IN2) and V_(REF),and that produce output signal V_(OUT) at output nodes 15 and 16. Inaddition, the circuit has a transistor 21 that receives an input signalV_(IN1). More specifically, node 15 is connected to the drain oftransistor 19 and node 16 is connected to the drain of transistor 20.The sources of transistors 19-20 are connected to a node 23. Node 23 isthen connected to the drain of transistor 21. Transistor 21 has itssource connected to ground via a current source 24. The gate oftransistor 19 receives an input signal V_(IN2). The gate of transistor20 receives an input signal V_(REF). The gate of transistor 21 receivesan input signal V_(IN1). Transistors 19-21 are N-channel transistors.Alternatively, transistors 19-21 can be P-channel transistors or bipolartransistors. For one embodiment, transistor 19 has a size that issubstantially equal to that of transistor 20.

As seen from FIG. 2, the V_(IN1) signal exhibits a full CMOS voltageswing. The V_(IN2) signal, however, is a small voltage swing signal thatoscillates substantially symmetrically around the V_(REF) referencevoltage. As can be seen from FIG. 2, the V_(REF) signal is a constant DCreference voltage. The V_(IN2) signal is therefore referred to asquasi-differential signal. In other words, the V_(IN2) and V_(REF)signals are not complementary to each other. The V_(IN1) and V_(IN2)signals are shown in the quadrature phase relationship in FIG. 2.

Alternatively, the V_(IN2) signal is a small swing, fully differentialsignal that swings between a V_(high) voltage and a V_(low) voltage. Inthis case, the V_(REF) signal is complementary to the V_(IN2) signal. Inother words, when the gate of transistor 19 receives the V_(high)voltage, the gate of transistor 20 receives the V_(low) voltage.

Transistors 19-21 detect the quadrature phase error of the V_(IN1) andV_(IN2) input signals. It is desirable to have the V_(IN1) and V_(IN2)signals in a quadrature phase relationship. When quadrature phase erroroccurs (i.e., the desired quadrature phase relationship has not beenachieved), phase detector 10 detects that condition by producing a netdifferential voltage across nodes 15-16 (i.e., the output V_(OUT)) atthe end of each measurement cycle. The amplitude of the net differentialvoltage across nodes 15-16 is a function of the amount of quadraturephase error between the V_(IN1) and V_(IN2) input signals. If phasedetector 10 does not detect any quadrature phase error, phase detector10 does not produce any net differential voltage across nodes 15-16 atthe end of the detection cycle.

Phase detector 10 also includes a transistor 22 coupled between nodes15-16. Transistor 22 is an N-channel MOSFET transistor. Alternatively,transistor 22 can be a P-channel MOSFET transistor or a bipolartransistor. Transistor 22 is used in phase detector 10 as an equalizingtransistor. Transistor 22 causes the voltage difference across nodes15-16 to be zero when transistor 22 conducts before a measurement cycleis initiated. As can be seen from FIG. 1, transistor 22 is switched onor off by the V_(EQ) signal. When transistor 22 is turned on by theV_(EQ) signal, nodes 15 and 16 are connected together via transistor 22and the voltages at nodes 15-16 are equalized.

FIG. 2 also illustrates the signal waveform of the V_(EQ) signal. As canbe seen from FIG. 2, the V_(EQ) signal can be a periodic pulse signalthat occurs before every pulse of the V_(IN1) signal. The V_(EQ) signalhelps to equalize the voltages across nodes 15-16 for starting adetection cycle. Alternatively, the pulse cycle of the V_(EQ) signal canoccur before every Nth pulse of the V_(IN1) signal.

Referring to FIGS. 1-2, the operation of phase detector 10 is nowdescribed. As shown in FIG. 1, transistor 21 connects a current I fromnode 23 to current source 24 when the V_(IN1) signal is at the highV_(DD) voltage, thereby enabling transistors 19 and 20 to charge ordischarge capacitances 17 and 18 as 11 will be described in more detailbelow. Because transistor 21 is connected to current source 24,transistor 21, when conducting, only allows the amount of current I toflow through. The V_(IN1) signal controls the start of each detectioncycle. Whenever the voltage level of the V_(IN1) signal rises to theV_(DD) voltage, a detection cycle is initiated.

When the voltage level of the V_(IN2) signal is higher than that of theV_(REF) voltage and when the V_(IN1) signal is at the V_(DD) voltage(e.g., from time t₁ to time t₂), transistor 19 conducts more thantransistor 20 does. Transistor 19 thus contributes substantially all theI current to node 23. Because each of nodes 15 and 16 receivessubstantially the same amount of current from the load element formed bytransistors 11-14, capacitor 17 is charged differently than capacitor 18if transistors 19 and 20 are not drawing the same amount of current tonode 23. In this case, capacitor 18 may be charging while capacitor 17is discharging. This in turn generates a differential voltage acrossnodes 15-16, and therefore at the output V_(OUT) Of phase detector 10.The differential voltage at the output V_(OUT) ramps linearly upwardsfor the time that the voltage of the V_(IN2) signal is higher than theV_(REF) reference voltage (e.g., from time t₁ to time t₂ in FIG. 2). Thesignal waveform of the V_(OUT) signal is also shown in FIG. 2.

When the voltage level of the V_(IN2) signal is lower than that of theV_(REF) voltage and when the V_(IN1) signal is at the V_(DD) voltage(e.g., from time t₂ to time t₃), transistor 20 then contributessubstantially all the I current to node 23. This in turn causes thecharging of capacitors 17-18 to be uneven. In this case, capacitor 17may be charging while capacitor 18 is discharging. This then results inthe differential voltage at the output V_(OUT) of phase detector 10 todrop linearly downwards (see the waveform of the V_(OUT) signal in FIG.2).

When the voltage level of the V_(IN1) signal goes to ground, at theconclusion of the detection cycle, transistor 21 disconnects current Ifrom node 23 and transistors 19 and 20 are thereby effectively disabledfrom charging or discharging capacitances 17 and 18. Because of this,the differential voltage at the output V_(OUT) stops changing. If theV_(IN1) and V_(IN2) signals are in perfect quadrature, the differentialvoltage across nodes 15-16 ramps linearly towards zero and no netdifferential voltage will be developed at the V_(OUT) output of phasedetector 10 at the time when the V_(IN1) signal goes to ground (e.g., attime t₃, after the detection cycle). If, however, a quadrature phaseerror exists between the V_(IN1) and V_(IN2) signals, a net differentialvoltage will be developed across nodes 15-16 at the end of the phasedetection cycle (e.g., from time t₁ to time t₃). The net differentialvoltage across nodes 15-16 is substantially proportional to the amountof the quadrature phase error.

The output V_(OUT) of phase detector 10 can be connected to a comparatorto generate a binary quadrature phase error output. Other circuits mayalso be used to generate the binary quadrature phase error output. FIG.5 shows an example of a comparator 100 connected to receive signalsV+_(OUT) and V−_(OUT) of FIG. 1, and to produce a binary quadraturephase error output 102.

The above description of phase detector 10 in detecting the quadraturephase error assumes the desirable situation in which the influence ofany parasitic capacitance of transistors 19 through 21 at node 23 isneglected. As can be seen from FIG. 1, phase detector 10, however,includes a parasitic capacitor 25 coupled between node 23 and ground.Parasitic capacitor 25 includes the parasitic capacitance associatedwith one or more of transistors 19-21 at node 23, as well as otherparasitic capacitances. Because transistor 21 is used as a switch,parasitic capacitor 25 includes the parasitic capacitance between thesource of transistor 21 and ground.

Due to the existence of parasitic capacitor 25 in the circuit of phasedetector 10, phase detector 10 generates a net differential voltage atthe output V_(OUT) of the circuit at the end of a detection cycle evenwhen the V_(IN1) and V_(IN2) signals are in the perfect quadrature phaserelationship, as can be seen from FIG. 2 (e.g., at time t₃). Thegeneration of the net differential voltage at the V_(OUT) output ofphase detector 10 by parasitic capacitor 25 is described below.

As can be seen from FIG. 1, due to parasitic capacitor 25, the voltagelevel at node 23 does not change immediately after transistor 21 isturned on by the V_(IN1) signal, causing the current flowing throughtransistor 21 to exceed the current I, which generates an additionalerror current. Because the voltage level of the V_(IN2) signal is higherthan the V_(REF) voltage, this additional error current flows throughtransistor 19. This in turn causes capacitor 17 to be additionallydischarged by the additional error current, which results in thedifferential voltage at the output V_(OUT) to be ramped higher.

When, however, the voltage level of the V_(IN2) signal drops below theV_(REF) voltage, transistor 19 is much less conducting than transistor20, and transistor 20 contributes substantially all the I current tonode 23. The voltage level at node 23 falls. This causes parasiticcapacitor 25 to be discharged, reducing the current flowing throughtransistor 20, which generates an additional error current flowingthrough transistor 20 to capacitor 18. This additional error currentcauses capacitor 18 to be additionally charged.

In addition, due to parasitic capacitor 25, the voltage level at node 23does not change immediately after transistor 21 is turned off by theV_(IN1) signal, causing an additional error current to flow throughtransistor 20 to parasitic capacitor 25. This additional error currentcauses capacitor 18 to be additionally discharged.

As a result, all the above-described error currents in chargingcapacitors 17-18 cause a net differential voltage at the output V_(OUT)of phase detector 10 at the end of a detection cycle even when theV_(IN1) and V_(IN2) signals are in the perfect quadrature phaserelationship, as can be seen from FIG. 2. When this occurs, a phasedetection error occurs. Because of the unpredictable nature of theparasitic capacitance, the voltage level of the net differential voltagedue to the parasitic capacitance also cannot be predicted.

Phase detector 40 of FIG. 3 eliminates the net differential voltageoccurring at the output of the circuit due to the parasitic capacitance.To accomplish this, the circuit of FIG. 3 includes error correctiontransistors 52 and 53 that are cross-coupled to the output nodes 45 and46 to reduce any output signal error induced by parasitic capacitance57. The configuration and operation of these transistors will beexplained in more detail below.

Node 45 is connected to capacitor 47 and capacitor 48 is connected tonode 46. The capacitance of capacitor 48 is substantially equal to thatof capacitor 47. Nodes 45-46 are then connected to a first circuitformed by transistors 49 through 51 and a second circuit formed bytransistors 52 through 54. Transistors 51 and 54 are then connected to acircuit 60, which essentially includes a first current source forproviding a first current I₁ through transistors 51 and a second currentsource for providing a second current I₂ through transistor 54, as canbe seen from FIG. 3. Both the I₁ and I₂ currents are generated andcontrolled by a I_(BIAS) current.

Circuit 60 generates the I₁ and I₂ currents. The value of the I₂ currentis smaller than that of the I₁ current. For one embodiment, the value ofthe I₂ current is in a range of 20% to 30% of the I₁ current. Foralternative embodiments, the value of the I₂ current can be larger orsmaller than 20% to 30% of the I₁ current.

For one embodiment, transistors 49-51 and 52-54 are N-channel MOSFETtransistors. For alternative embodiments, transistors 49-51 and 52-54can be P-channel MOSFET transistors or bipolar transistors. For oneembodiment, the size of each of transistors 52-53 is substantially equalto that of each of transistors 49-50 and the size of transistor 54 issubstantially equal to that of transistor 51.

Transistor 49 is connected to node 45 and node 55. Transistor 50 isconnected to nodes 46 and 55. Transistor 51 connects node 55 to groundvia the current source I₁ formed by circuit 60. Similarly, transistor 52is connected to node 46 and a node 56. Transistor 53 is connected tonodes 45 and 56. Transistor 54 connects node 56 to ground via thecurrent source I₂ formed by circuit 60. The gate of each of transistors51 and 54 receives the V_(IN1) signal. The gate of each of transistors49 and 52 receives the V_(IN2) signal and the gate of each oftransistors 50 and 53 receives the V_(REF) voltage. The V_(IN1) andV_(IN2) signals and the V_(REF) voltage are identical to those describedabove and shown in FIGS. 1-2. FIG. 4 also illustrates the signalwaveforms of these signals.

FIG. 3 also illustrates a parasitic capacitor 57 connected to node 55and ground and a parasitic capacitor 58 connected to node 56 and ground.Parasitic capacitor 57 includes the parasitic capacitance of transistors49-51 at node 55 and parasitic capacitor 58 includes the parasiticcapacitance of transistors 52-54 at node 56. Parasitic capacitor 57 alsoincludes other parasitic capacitances. Because transistor 51 is used asa switch, parasitic capacitor 57 includes the parasitic capacitancebetween the source of transistor 51 and ground. Likewise, parasiticcapacitor 58 also includes other parasitic capacitances. Becausetransistor 54 is used as a switch, parasitic capacitor 58 includes theparasitic capacitance between the source of transistor 54 and ground.

Transistors 49-51 detect the phase error of the V_(IN1) and V_(IN2)signals. Transistors 52-54 cancel the net differential voltage at theoutput V_(OUT) Of phase detector 40 due to parasitic capacitor 57 in thecircuit. As described above, each of transistors 52-53 has a size thatis substantially equal to that of each of transistors 49-50. Therefore,the capacitance of parasitic capacitor 58 is substantially equal to thatof parasitic capacitor 57. Due to the negative cancellation effect oftransistors 52-54, the additional error currents generated in thecircuit due to parasitic capacitors 57-58 cancel each other and phasedetector 40 of FIG. 3 does not experience any net differential voltagegenerated at the output V_(OUT) of the circuit due to the parasiticcapacitance. Because the capacitance of parasitic capacitors 57-58 issubstantially equal, the additional error currents associated withparasitic capacitors 57-58 are also substantially equal. Transistors49-50 and 52-53 are, however, cross-connected such that their respectivecontributions subtract from each other. This causes the additional errorcurrents to cancel each other. This thus allows phase detector 40 todetect the quadrature phase error of the V_(IN1) and V_(IN2) signalswith minimized phase detection error.

The operation of transistors 52-54 is described below, in conjunctionwith FIGS. 3 and 4. As can be seen from FIG. 3, when transistor 51 isturned on by the logical high V_(IN1) signal, the voltage level at node55 does not change immediately, causing the current flowing throughtransistor 51 to exceed the current 11, which generates an additionalerror current. Because the voltage level of the V_(IN2) signal is higherthan the V_(REF) voltage at this time, this additional error currentflows through transistor 49, causing capacitor 47 to be additionallydischarged. Meanwhile, because transistor 54 is also turned on by thelogical high V_(IN1) signal, the voltage level at node 56 does notchange immediately, which also generates an additional error currentflowing through transistor 54. As the voltage level of the V_(IN2)signal is higher than the V_(REF) voltage at this time, an additionalerror current flows through transistor 52, causing capacitor 48 to beadditionally discharged. Because the capacitance of parasitic capacitor57 is equal to that of parasitic capacitor 58, the additional errorcurrent that flows through transistor 52 is substantially equal to theadditional error current through transistor 49. Given that transistor 52is connected to node 46 while transistor 49 is connected to node 45, theadditional error current generated by transistor 52 cancels thatgenerated by transistor 49.

When the voltage level of the V_(IN2) signal is lower than that of theV_(REF) voltage, transistor 49 is much less conducting than transistor50 and transistor 52 is much less conducting than transistor 53. Thevoltage level at each of nodes 55 and 56 falls. This causes parasiticcapacitors 57 and 58 to be discharged, reducing the current flowingthrough transistors 50 and 53, respectively. This then causes anadditional error current to flow through transistor 50 to capacitor 48and an additional current to flow through transistor 53 to capacitor 47,additionally charging capacitors 47 and 48, respectively. Given thattransistor 50 is connected to node 46 and transistor 53 is connected tonode 45 and given that the additional error currents through transistors50 and 53 are substantially equal to each other, the additional chargingto each of capacitors 47 and 48 cancels each other.

In addition, due to parasitic capacitors 57 and 58, the voltage level ateach of nodes 55 and 56 does not change immediately after transistors 51and 54 are turned off by the V_(IN1) signal, causing an additional errorcurrent to flow through transistor 50 to parasitic capacitor 57 and anadditional error current to flow through transistor 53 to parasiticcapacitor 58. The additional error currents cause capacitors 47 and 48to be additional discharged, respectively. Because the capacitance ofparasitic capacitor 57 is substantially equal to that of parasiticcapacitor 58, the additional error current flowing through transistor 50is substantially equal to the additional error current flowing throughtransistor 53. Given that transistor 50 is connected to node 46 andtransistor 53 is connected to node 45, the additional error currentscancel each other. By doing so, no net differential voltage due toparasitic capacitor 58 will be developed at the output V_(OUT) and phasedetector 40 detects the quadrature phase error of the V_(IN1) andV_(IN2) signals with minimized detection error. The signal waveform ofthe V_(OUT) signal of phase detector 40 is shown in FIG. 4.

The V_(OUT) output of phase detector 40 can also be connected to acomparator to generate a binary quadrature phase error output.Alternatively, other circuits can be used to generate the binaryquadrature phase error output. FIG. 5 shows an example of a comparator100 connected to receive signals V+_(OUT) and V−_(OUT) of FIG. 3, and toproduce a binary quadrature phase error output 102.

Phase detector 40 also includes an equalizing transistor 59 connectedbetween nodes 45-46. Transistor 59 ensures that phase detector 40initiates a phase detection cycle with a zero differential voltage atthe output V_(OUT), and is controlled by the V_(EQ) signal.

The generation of the V_(EQ) signal can be controlled by a clock signal.Therefore, various clocking protocols can be used to generate the V_(EQ)signal pulses. For example, to increase sensitivity in someapplications, the measurement can take place over a number of clockcycles. In those cases, the V_(EQ) pulse is generated such thattransistor 59 is activated only once every N clock cycles, wherein N isthe number of clock cycles during which the phase error measurement isallowed to integrate.

For one embodiment, N is equal to two, as shown in FIG. 4. Foralternative embodiments, N can be larger than two.

Thus, the phase detector described above includes first and secondcircuits that are constructed in substantially the same way and receivethe same input signals. The first and second circuits are, however,cross-coupled together such that the error current generated by thesecond circuit cancels that generated by the first circuit in order toallow the circuit to perform the designated function with minimizederror.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention as setforth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

What is claimed is:
 1. A phase detection circuit, comprising: a firsttransistor to source a first current to a first node; a secondtransistor, coupled to the first transistor, to source a second currentto a second node, wherein the second current is mirrored from the firstcurrent; a third transistor to source a third current to the secondnode; a fourth transistor, coupled to the third transistor, to source afourth current to the first node, wherein the fourth current is mirroredfrom the third current; a first capacitance, coupled to the first node;a fifth transistor coupled between a current sink path and a third node,wherein the fifth transistor receives a first input signal, and wherein:the current sink path is coupled to the third node in response to afirst state of the first input signal; and the current sink path isisolated from the third node in response to a second state of the firstinput signal; a sixth transistor to couple the first capacitance to thethird node in response to a second input signal, wherein: the firstcapacitance is charged in a first direction when the first capacitanceis coupled to the current sink path; and the first capacitance ischarged in a second direction when the first capacitance is isolatedfrom the current sink path; and an output terminal coupled to the firstcapacitance, to indicate a quadrature phase error between the first andsecond input signals, wherein a voltage present at the first outputterminal after a detection cycle indicates a quadrature phase differencebetween the first and second input signals, wherein the detection cycleincludes charging the first capacitance in the first and seconddirections.
 2. A quadrature phase detection circuit as recited in claim1, further comprising a second capacitance coupled to the second node,wherein there is a net differential voltage across the first and secondcapacitances after the detection cycle.
 3. A quadrature phase detectioncircuit as recited in claim 1, further comprising a comparator that isresponsive to the voltage present at the first output terminal togenerate a binary quadrature phase difference output.
 4. A phasedetection circuit, comprising: a load circuit that includes first andsecond current mirrors cross coupled at respective first and secondnodes; a first transistor to receive a first input signal, wherein: thefirst transistor couples a current sink path to a third node in responseto a first state of the first input signal; and the first transistorisolates the current sink path from the third node in response to asecond state of the first input signal; a second transistor to activatea current path between the first node and the third node in response toa second input signal; a capacitance coupled to the first node, wherein:the capacitance is charged in a first direction when the current pathbetween the first node and the third node is activated and the firsttransistor couples the current sink path to the third node; and thecapacitance is charged in a second direction when the current pathbetween the first node and the third node is inactivated and the firsttransistor isolates the current sink path from the third node; and anoutput terminal coupled to the capacitor, wherein the charging of thecapacitance in the first and second directions produces a voltage at theoutput terminal that indicates an amount of quadrature phase differencebetween the first and second input signals.
 5. A quadrature phasedetection circuit as recited in claim 4, further comprising a comparatorthat is responsive to the voltage at the output terminal to generate abinary quadrature phase error output.
 6. A phase detection circuit,comprising: a load circuit that includes cross coupled first and secondcurrent mirrors, wherein the first current mirror sources a first pairof currents at a respective pair of nodes, and the second current mirrorsources a second pair of currents at the respective pair of nodes; afirst capacitor coupled to the load circuit; first and secondtransistors, coupled in series between the first capacitor and a firstcurrent source, wherein the first and second transistors are responsiveto respective first and second input signals to produce a quadraturephase error signal on an output terminal of the first capacitor, aftercharging and discharging the first capacitor.
 7. A quadrature phasedetection circuit as recited in claim 6, further comprising: a secondcapacitor coupled to the load circuit; a third transistor, coupled tothe second capacitor, wherein the third transistor receives a referencevoltage signal; and a fourth transistor coupled in series between thethird transistor and a second current source, wherein the fourthtransistor receives the first input signal.
 8. A quadrature phasedetection circuit as recited in claim 6, further comprising: a secondcapacitor coupled to the load circuit; a third transistor coupledbetween the second capacitor and the second transistor, wherein thethird transistor receives a reference voltage signal.
 9. A quadraturephase detection circuit as recited in claim 6, further comprising: asecond capacitor coupled to the load circuit; a third transistor coupledbetween the second capacitor and the second transistor, wherein thethird transistor receives a third input signal, and wherein the thirdinput signal is complementary to the second input signal.
 10. Aquadrature phase detection circuit as recited in claim 6, wherein: thefirst current mirror includes: a first transistor to source a firstcurrent of the first pair of currents to a first node of the pair ofnodes; and a second transistor, coupled to the first transistor, tosource a second current of the first pair of currents to a second nodeof the pair of nodes, wherein the second current of the first pair ofcurrents is mirrored from the first current of the second pair ofcurrents; and the second current mirror includes: a third transistor tosource a first current of the second pair of currents current to thesecond node; and a fourth transistor, coupled to the third transistor,to source a second current of the second pair of currents to the firstnode, wherein the first current of the second pair of currents ismirrored from the second current of the second pair of currents.
 11. Aquadrature phase detection circuit as recited in claim 6, wherein thefirst input signal includes a first voltage swing and the second inputsignal includes a second voltage swing, wherein the second voltage swingis less than the first voltage swing.